Embedded Control Systems Survival Guide

Compiled from Lectures 1, 3, 4, 7, 8, & 9. This is your mini-textbook, cheat sheet, and practice quiz rolled into one.

Designed for Focus & Retention

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The 12 Things You Must Know

Master these for the quiz.

1.

Flash vs SRAM
what goes where & why.

2.

Memory-mapped I/O
registers live at addresses.

3.

Address Bus
STM32 is 32-bit = 4GB space.

4.

Peripherals
controlled by registers (GPIO).

5.

stdint.h
uint8_t, uint16_t, uint32_t sizes.

6.

Pointers
store addresses, dereference to read/write.

7.

Pointer Size
depends on machine (PC vs STM32).

8.

const vs volatile
especially for hardware registers.

9.

Bitwise Ops
&, |, ^, ~, <<, >> and their uses.

10.

Masks + Shifts
extract fields from 32-bit values.

11.

Structs
. vs -> and why padding happens.

12.

Interrupt Flow
EXTI -> NVIC -> ISR -> HAL -> Callback.

1

Embedded + Memory Fundamentals

What "Memory-Mapped I/O" Means

On STM32, GPIO pins aren't magic pins — they're controlled by peripheral registers. Those registers are placed ("mapped") into the same address space as normal memory.

Key Takeaway: Your CPU can read/write them like variables.

Address Bus → Address Range

Your STM32 has a 32-bit address bus.

  • Range: 0x0000_0000 to 0xFFFF_FFFF
  • Capacity: 4,294,967,296 possible addresses ≈ 4 GB address space.

GPIO Registers You Should Recognize

Match the register name to its purpose:

MODER - Mode register
OTYPER - Output type
OSPEEDR - Speed
PUPDR - Pull-up/pull-down
IDR - Input read
ODR - Output write
BSRR - Bit set/reset

Also worth recognizing: AFRL/AFRH, LCKR, and related GPIO control registers.

2

Embedded C Survival Kit

2.1 stdint.h - Why Professors Love It

A plain int can be 2 bytes on one system and 4 bytes on another. stdint.h eliminates ambiguity and prevents hidden portability bugs.

  • uint8_t
    1 byte (8 bits)
  • uint16_t
    2 bytes (16 bits)
  • uint32_t
    4 bytes (32 bits)

2.2 Pointers

A pointer stores an address, not a value.

  • &x - address of x
  • *p - value at address p (dereference)

2.3 Pointer Size

Pointer size depends on the architecture's bus width.

On 64-bit systems, pointers are usually 8 bytes regardless of pointee type. They must be wide enough to hold any valid address.

  • PC (x86_64) 8 bytes
  • STM32 (32-bit) 4 bytes

Quiz trick: "Pointer size depends on architecture."

2.4 Casting Addresses

To treat a raw number as an address, typecast it.

// address of some register
uint32_t *reg = (uint32_t*) 0x40020000;
// write to that register
*reg = 0x1;
3

Bitwise Operations + Shifts

"Set/clear/check bits inside registers."

The Operators

  • & AND - masking/checking
  • | OR - setting bits
  • ^ XOR - toggling bits
  • ~ NOT - inverting bits
  • << >> Shifts - moving bits

4 Patterns to Memorize

Set bit n
REG |= (1U << n);
Clear bit n
REG &= ~(1U << n);
Toggle bit n
REG ^= (1U << n);
Check bit n
if (REG & (1U << n))

3.2 How Shifts Help Decode 32-Bit Packets

Moves the target field to bit 0, then mask isolates it.

Example: Extract Packet field [12:9] (4 bits)

  1. Shift right by 9.
  2. Mask 4 bits (0b1111 = 0xF).
field = (packet >> 9) & 0xF;

This shift-then-mask pattern is reused constantly when decoding packed 32-bit data fields.

4

Bare-Metal GPIO Mechanics

Controlling an LED (like PA5) requires writing peripheral registers.

4.1 Minimal Steps

1

Enable Peripheral Clock: Without it, the peripheral won't accept configurations.

2

Set Pin Mode: Use the MODER register to set to output.

3

Write HIGH/LOW: By writing to ODR or BSRR.

The MODER Concept (Frequent MCQ)

In STM32 GPIO, each pin uses two bits in MODER to select its mode (input, output, alternate, analog).

Example: Pin 5 uses bits [11:10]. Code often clears 2 bits then sets them.

5

Structures, Padding and Dot vs Arrow

5.1 Dot vs Arrow

. (Dot)

Use when you have a struct variable.

-> (Arrow)

Use when you have a pointer to a struct.

5.2 Padding & Packing

Compilers insert "padding" bytes so data aligns on natural boundaries. This wastes SRAM and creates unused gaps between members.

Packed Structures

__attribute__((packed)) removes padding. Saves memory, but may slow down access.

Structs + Bit-Fields

Useful for decoding 32-bit packets, reducing memory usage, and grouping related bits into named fields.

6

HAL Drivers

HAL (Hardware Abstraction Layer) lets you write portable code using APIs rather than raw addresses or manual register bit-manipulation.

STM32 header files already define peripheral base addresses and overlay structures used by HAL and low-level code.

6.2 HAL GPIO Init Pattern

  1. Create an initialization struct.
  2. Fill its fields (Pin, Mode, Pull, Speed).
  3. Call HAL_GPIO_Init() to configure registers.

6.3 "Handle" Structures

For complex peripherals (UART), HAL uses a handle to store:

  • Base register address (Instance)
  • Init parameters
  • Pointers to TX/RX buffers
  • Counters/state variables
Handle = State + Configuration
7

Interrupts

7.1 What Happens - Big Picture

An interrupt starts when EXTI detects a rising/falling edge.

EXTI signals NVIC NVIC sets pending bit NVIC checks priority Runs highest-priority ISR

The CPU then locates the ISR through the vector table and jumps to it.

7.2 HAL Interrupt Flow (Memorize This)

EXTI0_IRQHandler
IRQ Handler (main.c)
HAL_GPIO_EXTI_IRQHandler
Driver: Clears flags
HAL_GPIO_EXTI_Callback
User Code (main.c)
  • IRQ handler in main.c calls HAL's IRQ handler.
  • HAL IRQ handler clears interrupt flags and calls the callback.
  • The callback is where your response code runs (for example, toggling an LED).

7.3 Steps to Configure GPIO Interrupt

  1. 1 Configure pin as input
  2. 2 Select edge trigger
  3. 3 Enable EXTI (NVIC delivery)
  4. 4 Identify IRQ number
  5. 5 Set IRQ priority
  6. 6 Enable IRQ reception
  7. 7 Write IRQ handler

Interactive Simulators

Practice bit operations, packet field extraction, and interrupt flow with deterministic visuals.

7A. Bitwise Register Simulator

Set, clear, toggle, and check any bit in a 32-bit register.

Hex:

Dec:

Bin:

Before:

After: 

REG |= (1U << 5);

7B. Packet Decoder Simulator

Shift then mask a selected bit range from a 32-bit packet.

Shift step:

Mask step:

Extracted (dec):

Extracted (hex):

Width: bits

(packet >> 9) & 0xF

7C. Interrupt Flow Stepper

Validate each stage before advancing: EXTI -> NVIC -> ISR -> HAL -> Callback.

EXTI
NVIC
ISR
HAL Handler
Callback

EE 3314 One-Page Cheat Sheet

Condensed cram sheet for formulas, register meanings, and interrupt flow.

Bitwise Patterns

Set bit n:    REG |=  (1U << n);
Clear bit n:  REG &= ~(1U << n);
Toggle bit n: REG ^=  (1U << n);
Check bit n:  if (REG & (1U << n))

Field [h:l]:  (value >> l) & ((1U << (h - l + 1)) - 1)

GPIO Register Purpose Map

  • MODER -> pin mode (input/output/AF/analog)
  • OTYPER -> output type
  • OSPEEDR -> output speed
  • PUPDR -> pull-up/pull-down
  • IDR -> read input pin state
  • ODR -> write output state
  • BSRR -> atomic set/reset

Interrupt Chain

EXTI -> NVIC -> ISR -> HAL_GPIO_EXTI_IRQHandler -> HAL_GPIO_EXTI_Callback

  • EXTI detects edge, signals NVIC.
  • NVIC checks priority and dispatches IRQ.
  • ISR calls HAL IRQ handler.
  • HAL clears flags and invokes callback.

Common Formulas + Facts

  • 32-bit address space: 0x0000_0000 to 0xFFFF_FFFF
  • uint8_t/16_t/32_t are fixed-width integer types.
  • Pointer size depends on architecture (x86_64: 8 bytes, STM32: 4 bytes).
  • volatile prevents optimizer from removing hardware reads/writes.
  • . for struct variable, -> for pointer to struct.
  • Padding may make struct size larger than member sum.

Exam Mode

Timed assessment with per-topic scoring and post-exam recommendations.

Ready
Difficulty

Practice Quiz

A. Fill in the Blank

1. To prevent the compiler from optimizing out a hardware register variable, use the qualifier.

volatile

2. The STM32 address bus is [bits], so its address range is [start] to [end].

32 bits; 0x0000_0000; 0xFFFF_FFFF

3. The register used to read an input pin is .

IDR

4. EXTI detects a [edge] or [edge] edge on a GPIO input pin.

rising; falling

5. Use -> when you have a to a structure.

pointer

B. Multiple Choice

6. Which operator is best for toggling a single bit?

A) &
B) |
C) ^
D) ~

7. Which operator is commonly used for masking?

A) &
B) |
C) ^
D) <<

8. Which register is most directly associated with setting pin mode?

A) IDR
B) MODER
C) ODR
D) BSRR

9. NVIC primarily:

A) Converts analog to digital
B) Stores program code
C) Manages interrupt pending/priorities and dispatch
D) Configures GPIO pull-ups

10. Why can a struct take more bytes than the sum of its members?

A) Cache
B) Padding/alignment
C) Endianness
D) Optimization level

C. Short Calculation

11. Set bit 5 of REG (write the one-liner).

REG |= (1U << 5);

12. Clear bit 12 of REG.

REG &= ~(1U << 12);

13. Extract bits [12:9] from packet.

(packet >> 9) & 0xF;

14. If REG = 0b10110000, what is REG & 0b00010000 in binary?

0b00010000

Answer Key

  1. volatile
  2. 32; 0x0000_0000; 0xFFFF_FFFF
  3. IDR
  4. rising; falling
  5. pointer
  6. C
  7. A
  8. B
  9. C
  10. B
  11. REG |= (1U << 5);
  12. REG &= ~(1U << 12);
  13. (packet >> 9) & 0xF;
  14. 0b00010000

Last-Minute Tips

If you only have one pass before the quiz:

  • Memorize the bit patterns (set / clear / toggle / check).
  • Say out loud what each GPIO register does (MODER / IDR / ODR / BSRR).
  • Trace the interrupt chain: EXTI → NVIC → IRQ handler → HAL handler → callback.